United Microelectronics Corporation (UMC) and AP Memory Technology Corporation (AP Memory) said Oct. 22 their Gen2D capacitor designs reached initial functional validation, with package testing next for artificial intelligence and high-performance computing (HPC) systems.
The third-quarter milestone covered tape-out and initial functional validation for AP Memory’s S-SiCap Gen2D discrete silicon-capacitor designs, according to the companies. The next stage is a system-level assessment of performance and reliability in substrate packages with varying capacitance and operating-voltage requirements. The announcement included no test measurements or timetable.
UMC will provide deep trench capacitor (DTC) foundry technology and wafer manufacturing. AP Memory will handle silicon-capacitor designs and system integration. Depending on the system, capacitors could go in an advanced package’s landside, substrate or interposer. The companies are also considering interposers that contain capacitors and separate capacitors placed at the package landside.
The firms say AI and HPC applications are raising the power demands package designs must meet. They argue that placing capacitors near the computing die can shorten the route power travels, helping stabilize delivery and regulate voltage.
UMC’s technology portfolio includes DTC in its 2.5D and 3D integrated-circuit offerings and describes optional DTC integration with a 2.5D through-silicon interposer. GC Hung, UMC’s senior vice president, described the broader direction as “from board-level towards increasingly vertical power integration on the chip-level.”
Separately, AP Memory said Oct. 13 that its IPD discrete S-SiCap product category entered mass production in the second quarter of 2026. The Oct. 22 announcement named no customers or commercial terms for the Gen2D work. System-level testing in substrate packages is the next stated step, and the companies gave no completion date.
