Physical Analysis of Texas Instruments's DRA726 Jacinto 6 Eco SoC Processor for Automotive Infotainment with Estimation of its Manufacturing Cost and Selling Price with Forecast for the Coming Years

Dublin, Feb. 23, 2017 -- Research and Markets has announced the addition of the "Texas Instruments DRA726 Jacinto 6 Eco SoC Processor for Automotive Infotainment: Physical Analysis" report to their offering.

Infotainment in automotive is growing very quickly as people requiring more and more in-vehicle experiences. It is now one of the most important factor when choosing to buy a new car. Enhanced functions became ordinary in the high-end car segment, but a strong pressure to integrate the same kind of interfaces is now demanded for the entry-level and mid-level vehicles.

Texas Instruments, with the Jacinto 6 Eco processor family address these entry- to mid-level segments by providing a cost effective solution with feature-rich in-vehicle infotainment.

The DRA726 is a System-on-Chip (SoC) ables to deliver high-integrity audio, simultaneous multimedia streaming and device connectivity. It includes an ARM Cortex-A15 MPU, a C66x DSP, two ARM Cortex-M4 MPUs and many automotive interfaces to provide a cost-optimized BOM for automotive Tier 1s and car manufacturers.

The SoC is based on enhanced OMAP architecture integrated on a 28nm technology and is provided in a 760-ball BGA package featuring TI's Via Channel Array (VCA) technology. It is AEC-Q100 qualified with automotive grade 1 temperature (-40°C to +125°C).

The report provides a complete physical analysis of the DRA726 component with keys information on the packaging and the die (size, process, main blocks). It also provides an estimation of its manufacturing cost and selling price with forecast for the coming years.

Key Topics Covered:

1. Overview/Introduction

2. Company Profile

3. Physical Analysis
- Physical Analysis Methodology
- Package Analysis
-- Package view, dimensions & marking
-- Package Marking
-- Package cross-section
- Die Analysis
-- Die view, dimensions & marking
-- Die Delayering
-- Main Blocks Area Ratio
-- Die Process (CMOS Transistors, SRAM)
-- Die cross-section (Die thickness, Metal Layers, Transistor)
-- Die process characteristics

4. Cost Analysis
- Synthesis of the Cost Analysis
- Manufacturing Locations Hypotheses
-- Wafer Fabrication Unit
-- Packaging
-- Tests
- Component Cost Analysis
-- Wafer front-end cost
-- Probe Test & Dicing Cost
-- Die cost
-- Packaging Cost
-- Final Test Cost
-- Component Cost

5. Estimated Price Analysis
- Manufacturer Financial Ratios
- Estimated Sales Price

For more information about this report visit http://www.researchandmarkets.com/research/m6bc2r/texas_instruments

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