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Taiwan Semiconductor Manufacturing Co. (TSMC), the world’s leading contract chipmaker, is nearing completion of a cutting-edge chip packaging technology to meet surging demand for high-performance AI chips, according to Nikkei Asia.
TSMC is developing a square substrate packaging method, diverging from the current industry standard of round substrates. This new approach will allow more semiconductors to be integrated within a single chip, significantly boosting computing power — a critical need for generative AI applications. Small-scale production is expected to begin by 2027, with a dedicated production line under construction in Taoyuan, Taiwan.
Chip packaging is one of the final and most vital steps in semiconductor production. It involves encasing chips in a substrate to connect them into broader electronic systems. TSMC’s new packaging technique expands on its existing CoWoS (Chip-on-Wafer-on-Substrate) technology, which has already proven instrumental in AI chip development.
Major tech giants including Nvidia, AMD, Google, Amazon, and Broadcom rely on TSMC’s CoWoS solutions to power their AI hardware. As demand for generative AI continues to rise, so does the need for enhanced chip performance, making packaging innovations essential.
Over the past two years, TSMC has seen strong growth fueled by the AI boom and increasing global semiconductor demand. With its latest packaging innovation, TSMC aims to solidify its dominance in the AI chip manufacturing space and remain a pivotal force in the global semiconductor supply chain.
